1. Field of the Invention
The present invention relates to an analog multiplier for multiplying two analog signals and more particularly, to a four-quadrant analog multiplier formed on a semiconductor integrated circuit device, which is capable of low-voltage operation at a voltage as low as IV, wide input voltage range, and variable transconductance characteristics.
2. Description of the Prior Art
A conventional four-quadrant analog multiplier of this type is disclosed in detail in IEICE Transactions on Electronics, Vol. E76-C, No. 5, pp. 714-737 May 1993, which was developed by the inventor, K. Kimura. This conventional multiplier has a basic configuration as shown in FIG. 1.
In FIG. 1, input ends of a first squarer 1 are applied differentially with first and second input signal voltages V.sub.x and V.sub.y to be multiplied in opposite phases. In other words, the input ends of the first squarer 1 are applied with a voltage (V.sub.x -V.sub.y).
Similarly, input ends of a second squarer 2 are applied differentially with the first and second input signal voltages V.sub.x and V.sub.y in the same phase. In other words, the input ends of the second squarer 2 is applied with a voltage (V.sub.x +V.sub.y).
Output ends of the first squarer 1 are connected to output ends of the second squarer 2 in opposite phase. In other words, the output ends of the first and second squarers 1 and 2 are connected so that output currents I.sub.1.sup.+ and I.sub.1.sup.- of the first squarer 1 and output currents I.sub.2.sup.+ and I.sub.2.sup.- of the second squarer 2 are subtracted from each other, respectively.
Output currents I.sub.M.sup.+ and I.sub.M.sup.- of the multiplier are defined as (I.sub.1.sup.+ -I.sub.1.sup.-) and (I.sub.2.sup.+ -I.sub.2.sup.-), respectively.
The multiplication result of the first and second input signal voltages V.sub.x and V.sub.y is derived from a differential output current .DELTA.I of the multiplier, which is defined as .DELTA.I=I.sub.M.sup.+ -I.sub.M.sup.-.
With the conventional analog multiplier of FIG. 1, the linear behavior is typically defined by the following algebraic equation (1) as EQU .DELTA.I=.kappa.(V.sub.x +V.sub.y).sup.2 -.kappa.(V.sub.x -V.sub.y).sup.2 =4.kappa.V.sub.x V.sub.y ( 1)
where .kappa. is a transconductance constant.
It is seen from the equation (1) that the linear function is defined by the difference between the square of (V.sub.x +V.sub.y) and the square of (V.sub.x -V.sub.y).
The technique utilizing the equation (1) is well known as the "quarter-square technique", in which various multiplier made of two MOSFETs have been studied based on the fact that the MOSFET has the square-law characteristic.
An analog multiplier constitutes a functional circuit block essential for analog signal applications. Recently, semiconductor integrated circuits have been made finer and finer and as a result, their supply voltages have been decreasing from 5 V to 3.3 or 3 V or less. Under such a circumstance, low-voltage circuits that can operate at a low voltage such as 3 V or less has been required to be developed. In the case, the multiplier needs to have linear input voltage ranges as wide as possible.
Also, the Complementary Metal-Oxide-Semiconductor (CMOS) technology has become recognized to be the optimum process technology for Large Scale Integration (LSI), so that analog multipliers that can be realized on the LSI using the CMOS technology have been required.
The above conventional analog multiplier is not capable of low-voltage operation at a voltage less than 3 V because of its circuit configuration.
Also, the above conventional analog multiplier is capable of low-voltage operation if it is composed of MOS field-effect transistors (MOSFETs). However, it is preferred that the input voltage ranges with good linearity are as wide as possible.
Further, the transconductance characteristics cannot be adjusted in the above conventional analog multiplier.